This invention relates to integrated circuit memory cell arrays, and more particularly, to the partial reconfiguration of memory cell arrays in integrated circuits such as programmable logic devices.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. Programmable logic devices have programmable logic that may contain programmable elements that are used to store configuration data supplied by the user. Once loaded, programmable elements supply control signals to transistors in the programmable logic in order to configure the programmable logic to implement the desired logic function. Programmable elements may be memory cells in an array.
Configuration data may be supplied to the programmable logic device in the form of a configuration bit stream. After a first configuration bit stream has been loaded onto a programmable logic device, the programmable logic device may be reconfigured by loading a different configuration bit stream in a process known as reconfiguration. An entire set of configuration data is often loaded during reconfiguration. However, it would sometimes be advantageous to reconfigure only a portion of the configuration bits in a process known as partial reconfiguration. It may also be advantageous to allow other portions of the programmable logic to continue to continue operating (“operate through”) during the partial reconfiguration process.
It would therefore be desirable to be able to provide an integrated circuit memory cell array that allows partial reconfiguration to be performed while at the same time allowing the non-partially-reconfigured blocks and routing to “operate-through” the partial reconfiguration process.